The present invention relates to a computer architecture and in particular to an architecture that provides for exception handling with reduced demands for storage of the computer state.
Exceptions are occurrences during the execution of a computer program that interrupt the normal program flow dictated by the instructions themselves. Example exceptions include: arithmetic exceptions caused by an instruction whose executed results do not map into a valid range of the instruction output, for example a division by zero which does not map into a finite floating-point output. Another example would be an ASCII to integer conversion function receiving a non-numeric ASCII string (e.g. “cat”). Page faults, where a memory resource relied upon is unavailable (for example in high-speed memory), may also be considered a class of exceptions, as may other hardware interrupt occurrences.
An exception is normally handled by a special circuit of the computer processor which detects the exception in response by saving the state of the processor (e.g. processor registers) and jumping to an exception handler being a subroutine written to treat a specific exception. Page faults and other hardware interrupts are typically resolved (for example, a page fault is resolved by loading the necessary data from disk) and the program may resume from the point of the exception. Some exceptions, for example division by zero, may not be resolved.
Graphic processors use a computer architecture in which a large number of processing elements may operate in parallel on graphic tasks, for example, shading, rasterization, rotation and other geometric manipulations, to provide for graphic displays of data. The large number of processing elements used in a graphic processor is practical because each processing element is relatively simple. Graphic processors are normally used in conjunction with a conventional processor having separate memory from the memory of the graphic processor. Graphic operations are conducted through a series of steps in which the conventional processor moves data from its memory to the memory of the graphic processor and then, upon completion of the graphic processing, moves the data from the memory of the graphic processor back to its own memory.
Support for exception handling in graphic processors, for example to handle page faults, would permit merging of the memory models of the main computer processor and a graphic processor simplifying the use of the graphic processor system. The ability to incorporate exception handling into graphic processors, however, is hampered by the complex architectural state of the graphic processor. While saving the architectural state in a conventional processor requires saving and restoring a few tens of registers, in a graphic processor, saving the architectural state could require saving and storing hundreds and thousands of registers. Adding the necessary circuit to save this architectural state would largely defeat the simplified architecture of the processing units underlying the scalability of its architecture.